Enterprise Flash Technology in Perspective: Beyond IOPS Hype and Misrepresentations
Enterprise Flash Technology in Perspective: Beyond IOPS Hype and Misrepresentations
Dr. John R Busch, CTO and Founder
Before we dive into our Schooner Labs Enterprise Flash Technology Evaluation reports, let’s get some perspective. There is a lot of hype and misrepresentiation in the industry around flash. We think it should stop. It adds no value to users.
IOPS Wars and PC Processor-Frequency Wars: Lessons in Local Optimization with Diminishing Returns…
Today’s flash hype is akin to the days when PC micro-processor manufacturers focused on and advertised processor clock frequency, even though higher clock frequencies provided no significant benefit to most real applications or to the user experience. The same has been true of the hype around IOPS in the flash industry. Flash manufacturers have been chasing the max IOPS crown (with LSI in the lead at one million IOPS in a single dual-socket commodity server), even though the IOPS provided by these products greatly exceed the need of most applications in a balanced system configuration.
This is a classic story of local optimization with diminishing returns. We need to shift away from this thinking. We need to shift to understanding the applications and the datasets for which flash technology is a fit. We need to focus on the design of balanced system solutions for them.
Exploiting Parallelism and Cost Matters! We Learned This with Multi-core…
There have also been blatant mis-compares of flash component technologies that ignore relative costs and parallelism. For example, several microbenchmark results are reported comparing a $15,000 Fusion-io card directly with a single $750 Intel X25e SSD. But these benchmarks do not factor in the ability to utilize commodity SSDs in parallel. Do so with a properly-designed balanced system and you can achieve the IOPS required by many applications and data sets at a small fraction of the cost.
This is reminiscent of the misunderstandings when we created multi-core processors. Multi-core processors are optimized to exploit thread-level parallelism rather than optimizing for a single thread of instructions though instruction-level parallelism. The complex software and hardware-optimizing single-thread instruction streams in expensive, non-commodity processors continue to be justified in some very high-performance computing applications (HPC). But the mainstream of computing has shifted to computer systems based on multi-core processors, exploiting the thread-level parallelism possible in properly-tuned modern software. The effective cumulative real instruction throughput and cost benefits of easily replicating simple cores on a single die and the benefits of industry commoditization greatly outweigh any benefits from optimizing for single thread instruction-level parallelism through complex applications, compilers, and a multi-issue, out-of-order pipeline processor.
This is also the case with the evolution of enterprise flash technologies. There’s a clear shift away from proprietary discrete FPGA-based controllers requiring complex server-based driver software to simple, parallel, commodity self-managing ASIC-based flash building blocks.
Sound Basis for Analysis: an Open Benchmarking Manifesto
Let’s get the metrics right. Let’s understand which applications and workloads are a good fit for flash. Let’s identify appropriate benchmarks and normalized configurations. Let’s define appropriate experimental designs. Let’s understand enterprise flash technology trends. Let’s evaluate first- and new-generation products accordingly. We hope our up-coming Schooner Labs Enterprise Flash Technology Evaluation reports on enterprise flash will help move the industry in this direction.